1. Field of the Invention
The present invention refers to a multiple control unit for selectively connecting a plurality of peripheral units with a central processing unit, comprising a register for memorizing in corresponding cells a plurality of interruption signals generated by said peripheral units for interrupting said processing operations, a priority decoder connected with said register for arranging said interruption signals according to a priority order and for generating a predetermined code combination associated with a priority interruption signal, and a device for transmitting said predetermined code combination to said central unit.
2. Description of the Prior Art
It is known to connect a plurality of peripheral units with a central processing unit by means of corresponding control units adapted to handle the data flow between central and peripheral units.
But this solution is of no use for machines where dimensions and cost are more critical than the processing speed.
It is furthermore known to connect a plurality of peripheral units with a central unit by means of a single multiple control unit adapted to establish a priority order among the peripherals.
A known multiple control unit of such kind comprises a register for storing the interruptions and a delay circuit to prevent the interruption of lower priority from being stored in such register during a fixed time interval, until the processing operation related to the interruptions of higher priority are exhausted.
But such a control unit has the disadvantage of slow operation in handling the interruptions as the register inhibition duration must be at least equal to the time required to handle any interruption, whereby such a time is longer or equal to the time required to execute the processing operation of the maxima duration.
A multiple control unit is known wherein a register adapted to store the interruptions is sensed cyclically by a timer. An interruption is handled as soon as it is recognized by the timer; after this the timer continues to sense the register starting from the position subsequent to the one corresponding to the interruption handled.
But such a control unit has the disadvantage that an instruction of higher priority appearing after the timer has sensed the register position corresponding thereto, is recognized only when the timer has completed the sensing cycle.
Furthermore, both described control units have the disadvantage that the reset of the cells storing the interruptions is made in a specific manner by wires associated with the respective interruption causes. Consequently, the central unit is charged with a task of selecting the wire associated with the handled interruption.